Phase locked loop (PLL) circuits are widely used in disk drive read channels. In such applications the PLL must be running at no more than a 1 or 2% difference with respect to the anticipated frequency of the read signal. In order to keep the PLL in its free running mode within 1 or 2% of the anticipated frequency a second PLL operating in the frequency and phase lock mode is used as a frequency synthesizer to operate at a frequency which is within 1 or 2% of the anticipated frequency of the read signal. A MUX or other switching device is used to feed the signal from the second PLL to the input of the first, primary, PLL when no read is occurring and to feed the read signal to the input of the primary PLL when a read is taking place. While this assures that the primary PLL will lock in on the read .signal when called upon, it introduces other problems: the voltage controlled oscillator (VCO) in the primary PLL must be carefully tuned to a certain frequency which will be within .+-. 20% of the read signal frequency. This is not always practical because process deviations can normally vary the value of resistors by .+-.30% and of capacitors by .+-.20%. One way to deal with this is to laser trim or otherwise carefully trim to obtain the resonant center frequency.
Another approach is to implement the entire system using digital circuitry which is complex and costly. See U.S. Pat. No. 4,929,918. Another approach is to employ external calibration techniques and circuitry. "A 7 Mbytes (65 MHz), Mixed-Signal, Magnetic Recording Channel DSP Using Partial Response Signaling With Maximum Likelihood Detection", Philpon et at., IEEE Journal of Solid Circuits, Vol. 29, No. 3, March 1994. One shortcoming of all these approaches is that once the center frequency is set there is no way to easily adjust it as it drifts with temperature and voltage supply or as the required synthesizer clock frequency is changed by the user.